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data book 1 12.99 hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules 3.3 v sdram modules 144-pin so-dimm sdram modules pc100/pc133 32 mb, 64 mb & 128 mb density in cob technique this infineon module family are industry standard 144-pin 8-byte synchronous dram (sdram) small outline dual in-line memory modules (so-dimm) which are organized as x64 high speed memory arrays designed for use in non-parity applications. these so-dimms use cob (chip-on- board) technology. decoupling capacitors are mounted on the board. the dimms use optional serial presence detects implemented via a serial e 2 prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 144-pin so-dimms provide a high performance, flexible 8-byte interface in a 67.5 mm long footprint. ? 144-pin eight byte small outline dual-in-line synchronous dram modules for notebook applications ? one bank 4m 64 non-parity organization ? two bank 8m 64 and 16m 64 non-parity module organization ? suitable for use in pc100 and pc133 applications ? auto resingle + 3.3 v ( 0.3 v) power supply ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? decoupling capacitors mounted on substrate ? all inputs and outputs are lvttl compatible ? serial presence detect with e 2 prom ? uses cob (chip-on-board) technique ? 4096 refresh cycles every 64 ms ? gold contact pad ? this module family is fully pin and functional compatible with the latest intel so-dimm specification ? performance: -7.5 -8 unit pc133 3-3-3 pc100 2-2-2 f ck clock frequency (max.) 133 100 mhz t ac clock access time cas latency = 2 & 3 5.4 6 ns
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 2 12.99 note: all partnumbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: hys 64v16220gcdl-8-b, indicating rev.b dies are used for sdram components. product sprectrum organi- zation partnumber sdrams used row addr. bank select column addr. refresh period 4m 64 hys64v4220gcdl-7.5 4 4m 16 12 ba0, ba1 8 4k 64 ms 8m 64 hys64v8220gcdl-7.5 8 4m 16 12 ba0, ba1 8 4k 64 ms 16m 64 HYS64V16220GCDL-7.5 16 8m 8 12 ba0, ba1 9 4k 64 ms 4m 64 hys64v4220gcdl-8 4 4m 16 12 ba0, ba1 8 4k 64 ms 8m 64 hys64v8220gcdl-8 8 4m 16 12 ba0, ba1 8 4k 64 ms 16m 64 HYS64V16220GCDL-8 16 8m 8 12 ba0, ba1 9 4k 64 ms card dimensions organization pcb-board l h t [mm] 4m 64 l-dim-144-c8 67.60 25.40 3.80 8m 64 l-dim-144-c8 67.60 25.40 3.80 16m 64 l-dim-144-c9 67.60 25.40 3.80 pin definitions and functions a0 - a11 address inputs dqmb0 - dqmb7 data mask ba0, ba1 bank selects cs0 - cs3 chip select dq0 - dq63 data input/output v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out for presence detect cke0 clock enable n.c. no connection clk0 clock input CC
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 3 12.99 pin configuration pin# front side pin# back side pin# front side pin# back side 1 v ss 2 v ss 73 n.c. 74 clk1 3dq0 4dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 n.c. 78 n.c. 7 dq2 8 dq34 79 n.c. 80 n.c. 9 dq3 10 dq35 81 v dd 82 v dd 11 v dd 12 v dd 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 v dd 28 v dd 99 dq23 100 dq55 29 a0 30 a3 101 v dd 102 v dd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 v dd 114 v dd 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 v dd 46 v dd 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 v ss 56 v ss 127 dq27 128 dq59 57 n.c. 58 n.c. 129 v dd 130 v dd 59 n.c. 60 n.c. 131 dq28 132 dq60 61 clk0 62 cke0 133 dq29 134 dq61 63 v dd 64 v dd 135 dq30 136 dq62 65 ras 66 cas 137 dq31 138 dq63
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 4 12.99 block diagram: one bank 4m 64 sdram dimm module 67 we 68 cke1 139 v ss 140 v ss 69 cs0 70 (a12) 141 sda 142 scl 71 cs1 72 (a13) 143 v dd 144 v dd pin configuration (contd) pin# front side pin# back side pin# front side pin# back side spb04133 dq0-dq7 cs d0 dq0-dq7 dqmb0 cs0 clk1 10 pf sa0 scl sa1 sa2 sda e 2 prom (256 word x 8 bit) v cc v ss c 1 - c 4 d0-d3 d0-d3 note: all resistors are 10 w ldqm we we dqmb1 dq8-dq15 dq8-dq15 udqm dq0-dq7 cs d2 dq32-dq39 dqmb4 ldqm we dqmb5 dq40-dq47 dq8-dq15 udqm dq0-dq7 cs d1 dq16-dq23 dqmb2 ldqm we dqmb3 dq24-dq31 dq8-dq15 udqm dq0-dq7 cs d3 dq48-dq55 dqmb6 ldqm we dqmb7 dq56-dq63 dq8-dq15 udqm d0-d3 a0-a11, ba0, ba1 ras d0-d3 cas d0-d3 cke0 d0-d3 4 sdram clk0
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 5 12.99 block diagram: two bank 8m 64 sdram dimm module spb04134 sa0 scl sa1 sa2 sda e 2 prom (256 word x 8 bit) v cc v ss c 1 - c 4 d0-d7 d0-d7 note: all resistors are 10 w d0-d7 a0-a11, ba0, ba1 ras d0-d7 cas d0-d7 cke0 d0-d7 4 sdram clk0 clk1 4 sdram dq0-dq7 cs d0 dq0-dq7 dqmb0 cs1 ldqm we cs0 dqmb1 dq8-dq15 dq8-dq15 udqm dq0-dq7 d2 dq32-dq39 dqmb4 ldqm dqmb5 dq40-dq47 dq8-dq15 udqm dq0-dq7 d1 dq16-dq23 dqmb2 ldqm dqmb3 dq24-dq31 dq8-dq15 udqm dq0-dq7 d3 dq48-dq55 dqmb6 ldqm dqmb7 dq56-dq63 dq8-dq15 udqm dq0-dq7 d4 ldqm dq8-dq15 udqm dq0-dq7 d5 ldqm dq8-dq15 udqm dq0-dq7 d6 ldqm dq8-dq15 udqm dq0-dq7 d7 ldqm dq8-dq15 udqm we cs we cs we cs we cs we cs we cs we cs we
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 6 12.99 block diagram: two bank 16m 64 sdram dimm module spb04202 dq0-dq7 dqm d0 dq0-dq7 dqm d4 cs0 cs1 dq0-dq7 dqmb0 dq0-dq7 dq32-dq39 dqmb4 dqm cs d2 dq0-dq7 dqm d6 a0-a11, ba0, ba1 d0-d7 dd v ss v c ras, cas, we d0-d3 4 sdram clk0 2 e prom (256 word x 8 bit) sa1 sa0 sa2 scl sda dqmb1 dq8-dq15 dqmb5 dq40-dq47 dqm dq0-dq7 dqm dqm dqm dq0-dq7 dq0-dq7 dq0-dq7 dq56-dq63 dq48-dq55 dqmb6 dqmb7 dqmb3 dq24-dq31 dqmb2 dq16-dq23 dq0-dq7 dqm dqm dq0-dq7 d1 dq0-dq7 dq0-dq7 dqm dqm d5 dq0-dq7 dqm dq0-dq7 dq0-dq7 dqm dqm dq0-dq7 d3 dqm d7 d0-d7 d0-d7 d0-d15 cs cs cs cs cs cs cs cke1 d4-d7 cke0 clk1 4 sdram note: 1. dq wiring may differ than describes in this drawing, however dq/dqmb/cke/cs relationship must be maintained as shown. in this design each of the d0-d7 components are represented by two 8 m x 8 chips. these two chips effectively work as a single 8 m x 16 device. 2.
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 7 12.99 dc characteristics t a = 0 to 70 c; v ss =0v; v dd , v ddq =3.3v 0.3 v parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il C0.5 0.8 v output high voltage ( i out =C4.0ma) v oh 2.4 C v output low voltage ( i out = 4.0 ma) v ol C0.4v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) C20 20 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C20 20 m a capacitance t a = 0 to 70 c; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit 4m 64 max. 8m 64 max. 16m 64 max. input capacitance (a0 to a11, ba0, ba1) c i1 25 50 65 pf input capacitance (ras , cas , we ) c i2 35 50 75 pf input capacitance (clk0, clk1) c i3 35 35 58 pf input capacitance (cs0 , cs1 ) c i4 25 30 40 pf input capacitance (dqmb0 - dqmb7) c i5 10 15 15 pf input/output capacitance (dq0 - dq63) c io 25 25 50 pf input capacitance (scl, sa0 - 2) c sc 10 15 18 pf input/output capacitance c sd 888pf
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 8 12.99 notes 1. these parameters depend on the cycle rate. these values are measured at 100 mhz operation frequency. input signals are changed once during t ck , excepts for i cc6 and for stand-by currents when t ck =infinity. 2. these parameters are measured with continuous data stream during read access and all dq toggling. cl = 3 and bl = 4 are assumed and the v ddq current is excluded. operating currents per memory bank t a = 0 to 70 c, v dd = 3.3 v 0.3 v (recommended operating conditions unless otherwise noted) parameter test condition symbol 4m 64 8m 64 16m 64 unit note operating current t rc = t rc(min.) , t ck = t ck(min.) outputs open, burst length = 4, cl = 3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access C i cc1 260 520 1024 ma 1) precharge stand-by current in power down mode cs = v ih(min.) , cke v il(max.) t ck =min. i cc2p 4816ma 1) t ck = infinity i cc2ps 248 ma 1) precharge stand-by current in non-power down mode cs = v ih (min.) , cke 3 v ih(min.) t ck =min. i cc2n 70 140 280 ma 1) t ck = infinity i cc2ns 10 20 40 ma 1) no operating current t ck = min., cs = v ih(min.) , active state (max. 4 banks) cke 3 v ih(min.) i cc3n 90 180 360 ma 1) cke v il(max.) i cc3p 16 32 64 ma 1) burst operating current t ck =min., read command cycling C i cc4 200 400 800 ma 1), 2) auto refresh current t ck =min., auto refresh command cycling C i cc5 260 520 1040 ma 1) self refresh current self refresh mode, cke = 0.2 v C i cc6 1.6 3.2 6.4 ma 1)
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 9 12.99 ac characteristics 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 10 C C 10 10 C C ns ns C clock frequency cas latency = 3 cas latency = 2 f ck C C 133 100 C C 100 100 mhz mhz C access time from clock cas latency = 3 cas latency = 2 t ac C C 5.4 6 C C 6 6 ns ns 2), 3) clock high pulse width t ch 2.5 C 3 C ns C clock low pulse width t cl 2.5 C 3 C ns C transition time t t 0.3 1.2 0.5 10 ns C setup and hold parameters input setup time t is 1.5 C 2 C ns 4) input hold time t ih 0.8 C 1 C ns 4) power down mode entry time t sb C1 C 1 clk 4) power down mode exit setup time t pde 0.8 C 1 C clk 4) mode register set-up time t rsc 2C 2 C clkC common parameters row to column delay time t rcd 20 C 20 C ns 5) row precharge time t rp 20 C 20 C ns 5) row active time t ras 45 100k 50 100k ns 5) row cycle time t rc 67 C 70 C ns 5) activate (a) to activate (b) command period t rrd 14 C 16 C ns 5) cas (a) to cas (b) command period t ccd 1C 1 C clkC
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 10 12.99 refresh cycle refresh period (4096 cycles) t ref C64C 64msC self refresh exit time t srex 1C 1 C clk 6) read cycle data out hold time t oh 3C 3 C nsC data out to low impedance time t lz 1C 0 C nsC data out to high impedance time t hz 37 3 8 ns 7) dqm data out disable latency t dqz C2 C 2 clkC write cycle data input to precharge (write recovery) t wr 2C 2 C clkC dqm write mask latency t dqw 0C 0 C clkC ac characteristics (contd) 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max.
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 11 12.99 notes 1. an initial pause of 100 m s is required after power-up. then a precharge all banks command must be given followed by eight auto refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1 v/ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time ( t t C 0.5) ns must be added to this parameter. 4. if t t is longer than 1 ns, a time (t t C 1) ns must be added to this parameter. 5. whenever the refresh period has been exceeded, a minimum of two auto (crb) refresh commands must be given to wake-up the device. 6. self refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 7. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 12 12.99 spd-table for pc100 2-2-2 so-dimm modules byte# description spd entry value hex 4m 64 -8 8m 64 -8 16m 64 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs) C0c 4 number of column addresses C 08 08 09 5 number of dimm banks 1/2 01 02 02 6 module data width 64 40 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl = 3 10.0 ns a0 10 sdram access time from clock at cl = 3 6.0 ns 60 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s80 13 sdram width, primary x16 10 14 error checking sdram data width n/a/x8 00 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 2 04 18 supported cas latencies 2, & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes: general v dd tol +/C 10% 0e 23 sdram cycle time at cl = 2 10.0 ns a0 24 sdram access time from clock at cl = 2 6.0 ns 60 25 sdram cycle time at cl = 1 not supported ff 26 sdram access time from clock at cl = 1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay 16 ns 10 29 minimum ras to cas delay 20 ns 14 30 minimum ras pulse width 45 ns 2d 31 module bank density (per bank) 32 mb/64 mb 08 08 10 32 sdram input setup time 2 ns 20 33 sdram input hold time 1 ns 10 34 sdram data input setup time 2 ns 20 35 sdram data input hold time 1 ns 10
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 13 12.99 36-61 superset information Cff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 C df e0 e9 64-125 manufacturess information (optional) C ff 126 frequency specification pc100 64 64 64 127 details C 87 c7 c7 128+ unused storage locations C ff spd-table for pc100 2-2-2 so-dimm modules (contd) byte# description spd entry value hex 4m 64 -8 8m 64 -8 16m 64 -8
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 14 12.99 spd-table for pc133 3-3-3 so-dimm modules byte# description spd entry value hex 4m 64 -7.5 8m 64 -7.5 16m 64 -7.5 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs) C0c 4 number of column addresses C 08 08 09 5 number of dimm banks 1/2 01 02 02 6 module data width 64 40 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl = 3 7.5 ns 75 10 sdram access time from clock at cl = 3 5.4 ns 54 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s80 13 sdram width, primary x16 10 14 error checking sdram data width n/a/x8 00 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 2 04 18 supported cas latencies 2, & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes: general v dd tol +/C 10% 0e 23 sdram cycle time at cl = 2 10.0 ns a0 24 sdram access time from clock at cl = 2 6.0 ns 60 25 sdram cycle time at cl = 1 not supported ff 26 sdram access time from clock at cl = 1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay 14 ns 0f 29 minimum ras to cas delay 20 ns 14 30 minimum ras pulse width 45 ns 2d 31 module bank density (per bank) 32 mb/64 mb 08 08 10 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input setup time 1.5 ns 15 35 sdram data input hold time 0.8 ns 08
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 15 12.99 36-61 superset information Cff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 C 81 82 03 64-125 manufacturess information (optional) C ff 126 frequency specification pc133 64 64 64 127 details C 87 c7 c7 128+ unused storage locations C ff spd-table for pc133 3-3-3 so-dimm modules (contd) byte# description spd entry value hex 4m 64 -7.5 8m 64 -7.5 16m 64 -7.5
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 16 12.99 package outlines 32 & 64 mbyte so-dimm module package (144-pin, dual read-out, single in-line memory module) 1 2.54 min 0.25 max +/- 0.05 59 61 63,6 6,0 4,0 23.2 32.8 24.5 2 60 62 144 143 20,0 0,8 0,6 detail of contacts: 3,8 o 1,8 4,6 2,5 3,3 3,7 1.0 +0.1 - 25,40 67,6 dm144-c8.wmf 4mx64/8mx64 cob-sdram sodimm
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 17 12.99 gld09192 67.6 63.6 25.4 3.3 23.2 3.8 1 0.1 20 3.7 detail of contacts min. 2.54 0.25 max. 0.6 0.05 0.8 1 1.8 4 6 59 61 143 32.8 2.5 4.6 2 60 62 144 1.5 0.1 0.1 4 24.5 128 mbyte so-dimm module package (144-pin, dual read-out, single in-line memory module)
hys 64vx20(2)0gcdl 144-pin so-dimm sdram modules data book 18 12.99 rev changes: 12.98 4m x 64 version added, 128 mbyte version spd byte changed from 08h to 10h (x16 device), check sum adjusted. capacitance values according to measurments on samples adjusted 12.1.99 preliminary changed to final input capacitances adjusted 19.3.99 128 mb block diagram clarified 20.4.99 icc6 low-power versions reduced to 400 a * components infineon logo added 5.5.99 serial resistors for clock inputs and dummy loading corrected 21.7.99 some capacitance values changes due to new measured data 29.7.99 pc133 versions added 23.8.99 editorial changes made according to mr. lewbel findings pc133 byte 126 changed to 64h 27.8.99 drawing for c8 optimised, old drawing may be missleading 6.9.99 template from r&l 3.12.99 pc133 timing parameters changed according to intel pc133 specification

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